With the development of the semiconductor technology, integrated circuits with better performance and more powerful functions require a greater element density. Thus, the sizes of the elements and the spaces between the elements need to be scaled further.
However, the scaling of element sizes in an integrated circuit will inevitably impair the constant material properties and physical effects in the operation of the transistor or other components. Therefore, many new inventions have been introduced to the design of transistors so as to maintain the performances of the components at an appropriate level.
A significant effort to maintain performance of a field effect transistor is to enhance carrier mobility. When applying a voltage to a gate isolated from a channel through a very thin gate dielectric, the carrier mobility may affect the current that flows through the channel.
It is known that, based on the type of carriers and the direction of stress, a mechanical stress in a channel region of a field effect transistor (FET) may significantly increase or decrease the drift mobility of carriers. In an FET, a tensile stress may increase the electron drift mobility and decrease the hole drift mobility, which may advantageously improve the performance of an N-type metal oxide semiconductor (NMOS); and, a compressive stress may increase the hole drift mobility and decrease the electron drift mobility, which may advantageously improve the performance of a P-type metal oxide semiconductor (PMOS). In the existing art, a considerable number of structures and materials have been proposed for including a tensile stress or compressive stress in a semiconductor material. For example, in US2006/0160317, there is provided a solution of increasing the carrier mobility in a channel by depositing a stress layer and selectively etching all or a part of gate layers in a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
However, in the prior art, the drift mobility of carriers is changed generally by providing a separate stress layer or stress interface, which is disadvantageous for the continuous scaling of device sizes and leads to a complex manufacturing process. Furthermore, with the scaling of sizes of a semiconductor device, the size of channel regions is also reduced. Therefore, when a stress material expands, the added stress applied by the stressed material on the source and/or drain regions at opposing sides of the channel region is very limited. As a result, the performance of a MOSFET transistor, particularly of an N-type field effect transistor (N-FET), cannot be improved well, and accordingly, the performance of the complementary metal oxide semiconductor (CMOS) circuit is poor. Therefore, it is desired to provide a new method for manufacturing a semiconductor device, which is capable of increasing the carrier mobility in a channel region of an NMOS transistor without using a separate stress layer, and thereby decreasing sizes of the device and simplifying the manufacturing process.